In general, the term "domino logic" is used to refer to an arrangement of logic circuit stages which may, for example, be cascaded together in an integrated circuit array configuration. A signal may be inputted to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus a "domino" effect is achieved whereby signals are sequentially propagated through an array of "stages" or "domino blocks", and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage.
Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage. Accordingly, a domino arrangement allows a signal to be processed through a relatively complex logic function during a single clock cycle. That ability of a domino circuit obviates the need for plural clock cycles to process the input signals, and also decreases the overall processing time of the logic function.
Perhaps the biggest disadvantage to domino logic is that it is not a complete logic family, i.e. it is not possible to construct all logic functions using only domino circuits or blocks. The problem is that domino logic does not admit any inverting stages. Attempts to avoid this "inversion" problem by adding inverting stages to ordinary domino logic introduces signal race conditions which would not be present in a pure domino logic configuration. The term "race condition" characterizes a timing relation between two signals that must be met for the circuit to function correctly and reliably, and this race condition is not relaxed by slowing the clock frequency.
In the past, efforts have been made to overcome the inversion problem, but such efforts have not been totally successful. For example, where the clock signal to the domino logic block is delayed in order to prevent the domino block from evaluating until the negative input to the block has stabilized. However, if the delay introduced in the clock is not large enough, a race condition is introduced and the circuit will fail to function properly and reliably, and any extra delay of the clock which may be applied as a safety margin, also slows the evaluation function of the circuit by an equal amount.
In some domino circuits, various latching circuits have been implemented in an effort to latch and thereby isolate the domino output or stage output signal in order to avoid corrupting the output signal when the domino stage is precharging in preparation for receiving the next input signal for processing by the domino circuit. However in those designs, care must be taken to insure that the isolation of the output signal does not come at too high of a cost in terms of added gate delays and the resulting introduced added propagation delay time for the domino circuit.
Thus there is a need to provide an improved method and apparatus for the implementation of a domino logic circuit which combines a latch function within a domino block and does not introduce unacceptable or more than minimal added delays due to additional stages which may otherwise adversely affect the speed, timing or reliability of the ripple domino logic circuitry.